AVR Features and Registers
AVR
This study is based on tiny2313 so memory, I/O address may vary in other AVR chip.
Memory
Flash - Program Memory, an endurance of at least 10,000 write/erase cycles.
SRAM - Used by MCU for keeping stack , 0x0060 - 0x00DF
EEPROM - used for data storage in this memory, this is accessible by MCU and user by the burner, the endurance of at least 100,000 write/erase cycles. Not directly accessible. Accessing Registers - EEPROM Address Registers, the EEPROM Data Register, and the EEPROM Control Register
32x8 General Purpose Register - fast registers which are directly connected with ALU. 0x0000 - 0x001F
I/O Register - register for configuring I/O services and accessing data, 0x0020 - 0x005F
Clock Source
CKSEL3..0
SUT1..0 (the start-up times)
The device is shipped with CKSEL = “0100”, SUT = “10”, and CKDIV8 programmed. The default clock source setting is the Internal RC Oscillator with longest start-up time and an initial system clock prescaling of 8, resulting in 1.0 MHz system clock.
System Clock Prescalar
System Clock Prescalar
This feature can be used to decrease the system clock frequency and the power consumption when the requirement for processing power is low.
CLKPR – Clock Prescale Register
Power Management and Sleep Modes
MCU Control Register – MCUCR control bits for power management.
System Control and Reset
The ATtiny2313 has four sources of reset:
- Power-on Reset. The MCU is reset when the supply voltage is below the Power-on Reset threshold (VPOT).
- External Reset. The MCU is reset when a low level is present on the RESET pin for longer than the minimum pulse length.
- Watchdog Reset. The MCU is reset when the Watchdog Timer period expires, the Watchdog is enabled, and Watchdog Interrupt is disabled.
- Brown-out Reset. The MCU is reset when the supply voltage VCC is below the Brown-out Reset threshold (VBOT) and the Brown-out Detector is enabled. Selected by the BODLEVEL Fuses.
MCU Status Register – MCUSR
WDRF: Watchdog Reset Flag
BORF: Brown-out Reset Flag
EXTRF: External Reset Flag
PORF: Power-on Reset Flag
Watchdog Timer
During normal operation, the computer regularly resets the watchdog timer to prevent it from elapsing, or "timing out". The Watchdog Timer (WDT) is a timer counting cycles of a separate on-chip 128 kHz oscillator. In Interrupt mode, the WDT gives an interrupt when the timer expires. This interrupt can be used to wake the device from sleep-modes, and also as a general system timer. In System Reset mode, the WDT gives a reset when the timer expires.
Interrupt and System Reset mode, combines the other two modes by first giving an interrupt and then switch to System Reset mode. This mode will for instance allow a safe shutdown by saving critical parameters before a system reset.
Watchdog Timer Control and Status Register - WDTCSR
EEPROM
When the EEPROM is read, the CPU is halted for four clock cycles before the next instruction is executed. When the EEPROM is written, the CPU is halted for two clock cycles before the next instruction is executed.
Address Register - EEAR
The initial value of EEAR is undefined. A proper value must be written before the EEPROM may be accessed. The EEPROM data bytes are addressed linearly between 0 and 127.
Data Register – EEDR
Control Register – EECR
Programming Mode Bits: EEPM1 and EEPM0 - Erase & Write in one operation, Erase, Write
Ready Interrupt Enable : EERIE - Interrupt generates a constant inter- rupt when Non-volatile memory is ready for programming.
Master Program Enable - The EEMPE bit determines whether writing EEPE to one will have effect or not.
Program Enable - The EEMPE bit must be written to one before a logical one is written to EEPE, otherwise no EEPROM write takes place. When the write access time has elapsed, the EEPE bit is cleared by hardware.
Read Enable: EERE - EERE bit must be written to one to trigger the EEPROM read. If a write operation is in progress, it is neither possible to read the EEPROM, nor to change the EEAR Register.
Fuse Bits & Lock Bits
32x8 General Purpose Register
All the 32 registers are directly connected to the Arithmetic Logic Unit (ALU), allowing two independent registers to be accessed in one single instruction executed in one clock cycle.
Six of the 32 registers can be used as three 16-bit indirect address register pointers for Data Space addressing – enabling efficient address calculations. One of these address pointers can also be used as an address pointer for lookup tables in Flash program memory. These added function registers are the 16-bit X-, Y-, and Z-register.
Each register is also assigned a data memory address, mapping them directly into the first 32 locations of the user Data Space. Address: 0x00 - 0x1F, last 6 address are X, Y, Z.
X, Y, Z have the functions as fixed displacement, automatic increment, and automatic decrement.
Stack
During interrupts and subroutine calls, the return address Program Counter (PC) is stored on the Stack. The Stack is effectively allocated in the general data SRAM, and consequently, the Stack size is only limited by the total SRAM size and the usage of the SRAM. All user programs must initialize the SP in the Reset routine (before subroutines or interrupts are executed). The Stack Pointer (SP) is read/write accessible in the I/O space.
The data SRAM can easily be accessed through the five different addressing modes supported in the AVR architecture. The memory spaces in the AVR architecture are all linear and regular memory maps.
Interrupt
A flexible interrupt module has its control registers in the I/O space with an additional Global Interrupt Enable bit in the Status Register. All interrupts have a separate Interrupt Vector in the Interrupt Vector table. The interrupts have priority in accordance with their Interrupt Vector position. The lower the Interrupt Vector address, the higher the priority.
When an interrupt occurs, the Global Interrupt Enable I-bit is cleared and all interrupts are disabled. The user software can write logic one to the I-bit to enable nested interrupts.
There are basically two types of interrupts.
The first type is triggered by an event that sets the interrupt flag. If an interrupt condition occurs while the corresponding interrupt enable bit is cleared, the interrupt flag will be set and remembered until the interrupt is enabled. Similarly, if one or more interrupt conditions occur while the Global Interrupt Enable bit is cleared, the corresponding interrupt flag(s) will be set and remembered until the Global Interrupt Enable bit is set, and will then be executed by order of priority.
The second type of interrupts will trigger as long as the interrupt condition is present. These interrupts do not necessarily have interrupt flags.
When the AVR exits from an interrupt, it will always return to the main program and execute one more instruction before any pending interrupt is served.
MCU Control Register – MCUCR
ISC11, ISC10: Interrupt Sense Control 1 Bit 1 and Bit 0
General Interrupt Mask Register – GIMSK
External Interrupt Flag Register – EIFR
Pin Change Mask Register – PCMSK
Interrupt Response Time
The interrupt execution response for all the enabled AVR interrupts is four clock cycles minimum. During this four clock cycle period, the Program Counter is pushed onto the Stack. The vector is normally a jump to the interrupt routine, and this jump takes three clock cycles.
If an interrupt occurs during execution of a multi-cycle instruction, this instruction is completed before the interrupt is served.
If an interrupt occurs when the MCU is in sleep mode, the interrupt execution response time is increased by four clock cycles. This increase comes in addition to the start-up time from the selected sleep mode.
A return from an interrupt handling routine takes four clock cycles. During these four clock cycles, the Program Counter (two bytes) is popped back from the Stack, the Stack Pointer is incremented by two, and the I-bit in SREG is set.
Stack Pointer
The Stack is mainly used for storing temporary data, for storing local variables and for storing return addresses after interrupts and subroutine calls. The Stack Pointer Register always points to the top of the Stack. Note that the Stack is implemented as growing from higher memory locations to lower memory locations.
The Stack Pointer is decremented by one when data is pushed onto the Stack and is decremented by two when the return address is pushed onto the Stack with subroutine call or interrupt.
The Stack Pointer is incremented by one when data is popped from the Stack and is incremented by two when data is popped from the Stack with return from subroutine RET or return from interrupt RETI.
- The Idle mode stops the CPU while allowing the SRAM, Timer/Counters, and interrupt system to continue functioning.
- The Power-down mode saves the register contents but freezes the Oscillator, disabling all other chip functions until the next interrupt or hardware reset.
- In Standby mode, the crystal/resonator Oscillator is running while the rest of the device is sleeping. This allows very fast start-up combined with low-power consumption.
GPIO
The ports are bidirectional I/O ports with optional internal pull-ups. Each port pin consists of three register bits: DDxn, PORTxn, and PINxn. The DDxn bit in the DDRx Register selects the direction of this pin. If DDxn is written logic one, Pxn is configured as an output pin. If DDxn is written logic zero, Pxn is configured as an input pin.
If PORTxn is written logic one when the pin is configured as an input pin, the pull-up resistor is activated.
Timer/Counter/PWM
Registers
The Timer/Counter (TCNT0) and Output Compare Registers (OCR0A and OCR0B) are 8-bit registers. Interrupt request (abbreviated to Int.Req. in the figure) signals are all visible in the Timer Interrupt Flag Register (TIFR). All interrupts are individually masked with the Timer Interrupt Mask Register (TIMSK).
Timer/Counter Clock Sources
The Timer/Counter can be clocked by an internal or an external clock source. The clock source is selected by the Clock Select logic which is controlled by the Clock Select (CS02:0) bits located in the Timer/Counter Control Register (TCCR0B).
Counter Unit
The main part of the 8-bit Timer/Counter is the programmable bi-directional counter unit.
The 8-bit comparator continuously compares TCNT0 with the Output Compare Registers (OCR0A and OCR0B). Whenever TCNT0 equals OCR0A or OCR0B, the comparator signals a match. A match will set the Output Compare Flag (OCF0A or OCF0B) at the next timer clock cycle. If the corresponding interrupt is enabled, the Output Compare Flag generates an Output Compare interrupt.
The OCR0x Registers are double buffered when using any of the Pulse Width Modulation (PWM) modes. For the normal and Clear Timer on Compare (CTC) modes of operation, the double buffering is disabled. The double buffering synchronizes the update of the OCR0x Compare Registers to either top or bottom of the counting sequence. The synchronization prevents the occurrence of odd-length, non-symmetrical PWM pulses, thereby making the output glitch-free.
The Waveform Generator uses the COM0x1:0 bits differently in Normal, CTC, and PWM modes.
Modes of Operation
Normal Mode
The simplest mode of operation is the Normal mode (WGM02:0 = 0). In this mode the counting direction is always up (incrementing), and no counter clear is performed. The counter simply overruns when it passes its maximum 8-bit value (TOP = 0xFF) and then restarts from the bottom (0x00).
The TOV0 Flag in this case behaves like a ninth bit, except that it is only set, not cleared. However, combined with the timer overflow interrupt that automatically clears the TOV0 Flag, the timer resolution can be increased by software.
Clear Timer on Compare Match (CTC) Mode
In Clear Timer on Compare or CTC mode (WGM02:0 = 2), the OCR0A Register is used to manipulate the counter resolution. In CTC mode the counter is cleared to zero when the counter value (TCNT0) matches the OCR0A. The OCR0A defines the top value for the counter, hence also its resolution.
An interrupt can be generated each time the counter value reaches the TOP value by using the OCF0A Flag. If the interrupt is enabled, the interrupt handler routine can be used for updating the TOP value.
Since the CTC mode does not have the double buffering feature. If the new value written to OCR0A is lower than the current value of TCNT0, the counter will miss the Compare Match.
Fast PWM Mode
The fast Pulse Width Modulation or fast PWM mode (WGM02:0 = 3 or 7) provides a high frequency PWM waveform generation option. The fast PWM differs from the other PWM option by its single-slope operation. The counter counts from BOTTOM to TOP then restarts from BOTTOM.
Due to the single-slope operation, the operating frequency of the fast PWM mode can be twice as high as the phase correct PWM mode that use dual-slope operation. This high frequency makes the fast PWM mode well suited for power regulation, rectification, and DAC applications.
Phase Correct PWM Mode
The phase correct PWM mode (WGM02:0 = 1 or 5) provides a high resolution phase correct PWM waveform generation option. The phase correct PWM mode is based on a dual-slope operation. The counter counts repeatedly from BOTTOM to TOP and then from TOP to BOTTOM.
In phase correct PWM mode the counter is incremented until the counter value matches TOP. When the counter reaches TOP, it changes the count direction.
Timer/Counter Control Register A – TCCR0A
COM0A1:0: Compare Match Output A Mode - Toggle/Set/Clear OC0A on Compare Match
WGM01:0: Waveform Generation Mode - PWM / CTC / Phase Correct PWM
Timer/Counter Control Register B – TCCR0B
WGM02: Waveform Generation Mode
CS02:0: Clock Select
USART
The three main parts of the USART (listed from the top): Clock Generator, Transmitter and Receiver.
The Clock Generation logic consists of synchronization logic for external clock input used by synchronous slave operation, and the baud rate generator. The XCK (Transfer Clock) pin is only used by synchronous transfer mode.
The Transmitter consists of a single write buffer, a serial Shift Register, Parity Generator and Control logic for handling different serial frame formats.
The Receiver is the most complex part of the USART module due to its clock and data recovery units. The recovery units are used for asynchronous data reception. In addition to the recovery units, the Receiver includes a Parity Checker, Control logic, a Shift Register and a two level receive buffer (UDR).
Clock Generation
The USART supports four modes of clock operation: Normal asynchronous, Double Speed asynchronous, Master synchronous and Slave synchronous mode.
The UMSEL bit in USART Control and Status Register C (UCSRC) selects between asynchronous and synchronous operation.
Double Speed (asynchronous mode only) is controlled by the U2X found in the UCSRA Register.
When using synchronous mode (UMSEL = 1), the Data Direction Register for the XCK pin (DDR_XCK) controls whether the clock source is internal (Master mode) or external (Slave mode). The XCK pin is only active when using synchronous mode.
USART Baud Rate Register (UBRR)
The USART Character SiZe (UCSZ2:0) bits select the number of data bits in the frame. The USART Parity mode (UPM1:0) bits enable and set the type of parity bit. The selection between one or two stop bits is done by the USART Stop Bit Select (USBS) bit.
Frame
The USART accepts all 30 combinations of the following as valid frame formats:
- 1 start bit
- 5, 6, 7, 8, or 9 data bits
- no, even or odd parity bit
- 1 or 2 stop bits
The TXC flag can be used to check that the Transmitter has completed all transfers, and the RXC flag can be used to check that there are no unread data in the receive buffer.
Transmission
The USART Transmitter is enabled by setting the Transmit Enable (TXEN) bit in the UCSRB Register. The baud rate, mode of operation and frame format must be set up once before doing any transmissions.
If 9-bit characters are used (UCSZ = 7), the ninth bit must be written to the TXB8 bit in UCSRB before the low byte of the character is written to UDR.
The USART Transmitter has two flags that indicate its state: USART Data Register Empty (UDRE) and Transmit Complete (TXC). Both flags can be used for generating interrupts.
When the Data Register Empty Interrupt Enable (UDRIE) bit in UCSRB is written to one, the USART Data Register Empty Interrupt will be executed as long as UDRE is set (provided that global interrupts are enabled). UDRE is cleared by writing UDR. When interrupt-driven data transmission is used, the Data Register Empty interrupt routine must either write new data to UDR in order to clear UDRE or disable the Data Register Empty interrupt, otherwise a new inter- rupt will occur once the interrupt routine terminates.
The Transmit Complete (TXC) flag bit is set one when the entire frame in the Transmit Shift Register has been shifted out and there are no new data currently present in the transmit buffer. The TXC flag bit is automatically cleared when a transmit complete interrupt is executed, or it can be cleared by writing a one to its bit location.
When the Transmit Complete Interrupt Enable (TXCIE) bit in UCSRB is set, the USART Transmit Complete Interrupt will be executed when the TXC flag becomes set (provided that global interrupts are enabled). When the transmit complete interrupt is used, the interrupt handling routine does not have to clear the TXC flag, this is done automatically when the interrupt is executed.
Data Reception
The USART Receiver is enabled by writing the Receive Enable (RXEN) bit in the UCSRB Register to one.
The Receive Complete (RXC) flag indicates if there are unread data present in the receive buffer. This flag is one when unread data exist in the receive buffer, and zero when the receive buffer is empty. If the Receiver is disabled (RXEN = 0), the receive buffer will be flushed and consequently the RXC bit will become zero.
Then the Receive Complete Interrupt Enable (RXCIE) in UCSRB is set, the USART Receive Complete interrupt will be executed as long as the RXC flag is set (provided that global interrupts are enabled). When interrupt-driven data reception is used, the receive complete routine must read the received data from UDR in order to clear the RXC flag, otherwise a new interrupt will occur once the interrupt routine terminates.
Receiver Error Flags
The USART Receiver has three error flags: Frame Error (FE), Data OverRun (DOR) and Parity Error (UPE). All can be accessed by reading UCSRA.
Asynchronous Data Reception
The USART includes a clock recovery and a data recovery unit for handling asynchronous data reception. The clock recovery logic is used for synchronizing the internally generated baud rate clock to the incoming asynchronous serial frames at the RxD pin.
Multi-processor Communication Mode
Setting the Multi-processor Communication mode (MPCM) bit in UCSRA enables a filtering function of incoming frames received by the USART Receiver. Frames that do not contain address information will be ignored and not put into the receive buffer.
Address/Data Identification
If the Receiver is set up to receive frames that contain 5 to 8 data bits, then the first stop bit indicates if the frame contains data or address information. If the Receiver is set up for frames with nine data bits, then the ninth bit (RXB8) is used for identifying address and data frames. When the frame type bit (the first stop or the ninth bit) is one, the frame contains an address. When the frame type bit is zero the frame is a data frame.
Each Slave MCU reads the UDR Register and determines if it has been selected. If so, it clears the MPCM bit in UCSRA, otherwise it waits for the next address byte and keeps the MPCM setting.
USART I/O Data Register – UDR
USART Control and Status Register A – UCSRA
USART Control and Status Register B – UCSRB
USART Control and Status Register C – UCSRC
USART Baud Rate Registers – UBRRL and UBRRH
Universal Serial Interface – USI
Three-wire Mode
The USI Three-wire mode is compliant to the Serial Peripheral Interface (SPI) mode 0 and 1, but does not have the slave select (SS) pin functionality. However, this feature can be implemented in software if necessary. Pin names used by this mode are: DI, DO, and USCK.
Two-wire Mode
The USI Two-wire mode does not incorporate slew rate limiting on outputs and input noise filtering. Pin names used by this mode are SCL and SDA. The main differences between the Master and Slave operation at this level, is the serial clock generation which is always done by the Master, and only the Slave uses the clock control unit. Clock generation must be implemented in software.
USI Data Register – USIDR
USI Status Register – USISR
USI Control Register – USICR
Analog Comparator
The Analog Comparator compares the input values on the positive pin AIN0 and negative pin AIN1. When the voltage on the positive pin AIN0 is higher than the voltage on the negative pin AIN1, the Analog Comparator output, ACO, is set. The comparator can trigger a separate interrupt, exclusive to the Analog Comparator. The user can select Interrupt triggering on comparator output rise, fall or toggle.
Analog Comparator Control and Status Register – ACSR
Digital Input Disable Register – DIDR
AVR development support in xcode
download above project and update the mpc library url in mkdist.sh
then run ./mkdist.sh
which will download and install all necessary files - avrgcc, avrdude, xcode project profile, etc
Now you can open AVR projects in xcode.
https://www.obdev.at/products/crosspack/index.html
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